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1/14 february 2001 AN1269 application note connecting the mpc555 microcontroller to the m58bf008 series flash memory contents n introduction n advantages of flash n m58bf008 bus architecture n mpc555 bus architecture C booting the mpc555 from external flash n mpc555 to m58bf008 connection C mpc555 bus configura- tion registers n example bus operations C asynchronous read ex- ample C synchronous burst read example C asynchronous write ex- ample C synchronous write ex- ample n stmicroelectronics software drivers n conclusion introduction this application note describes a method of to connecting the m58bf008 flash memory to the mpc555 microcontroller. the m58bf008 is an advanced 8 mbit flash memory from stmi- croelectronics, which can be configured as 256 kbit x32 bus width. the memory includes a burst interface for high speed access, allowing code to be executed directly from the memory without the need to shadow the code in ram. the mpc555 is a member of motorolas powerpc family of in- tegrated microprocessors. it is a general purpose 32-bit micro- controller with a wide variety of application areas but it particularly targeted towards automotive applications. advantages of flash flash memories can be used to store both code and data for the mpc555 microcontroller. unlike eproms the data in flash memories can be changed by the microcontroller. this enables non-volatile user data to be stored in the flash. field upgrades of the application code can be performed without any disas- sembly, unlike eprom solutions. it is usual to write separate boot and application programs so that the application program can be upgraded without changing the boot program. if the upgrade fails then the processor will still boot and it will be possible to reattempt to upgrade the ap- plication. the boot code can be programmed into the flash be- fore the flash is fitted to the circuit board or debug port can be used to boot the microcontroller and then program the flash. the m58bf008 flash memory has a special block, called the overlay block, that can be used to store the boot program. this is an extra 32 kbyte block that is mapped in place of block 0 on reset. the mpc555 can boot from this block, then disable it, giving access to block 0. the memory is 8 mbit plus 256 kbit in size. m58bf008 bus architecture consider the bus on the m58bf008, figure 1 shows the logic diagram. the memory has separate address and data buses that can connect directly to the address and data buses on the mpc555. there are several control lines required for burst ac- cess, these are chip enable (e ), output enable (g ), write en- able (w ), system clock (clk), load burst address (lba ), write/read (w r) burst address advance (baa ) and output disable (gd ). also, reset/power-down (rp ) is present.
AN1269 - application note 2/14 figure 1. m58bf008 logic diagram a burst read cycle is initiated on the rising edge of the system clock when chip enable is low to select the memory, a valid address is on the address inputs, latch burst address is low to latch the address and write/read is high to indicate a read. chip enable and write/read should remain constant through- out the read operation, whereas load burst address should only be low during the cycle where the ad- dress is latched, after that the address can change. output enable must be low to read the data when it becomes valid (after the x-latency) and burst address advance must be low to increase the address and output new data after the y-latency expires. the memory controller in the mpc555 can be configured to generate these signals without glue logic. unlike most ram options, it is not possible to write a single byte or a single 16-bit word to the memory. only 32-bit writes are supported. (this applies equally to reads, but, for a read, the unwanted data can be discarded). commands are written on dq0-dq7 to the memory, with dq8-dq31 being ignored; the dou- ble-words are written to the memory array as part of the program operation. the reset/power-down pin (rp ) should be held high for normal operation of the memory, this is the mem- orys non-reset state. to ensure that the overlay block is always read during the boot process and the memory is always in its read mode the reset/power-down should be low when the mpc555 is reset. the memory can be placed in a low-power mode by holding reset/power-down low; after reset/power-down is brought high again the memory returns to its reset state and may require configuration before being accessed correctly. in asynchronous modes several pins are not used and their voltage is dont care. these are clk, lba , w r and baa . during asynchronous accesses the cpu does not need to control these pins, they can be tied to v il or v ih , or change through the access. this may be useful when trying to replace another mem- ory with an m58bf008. 18 a17-a0 clk dq31-dq0 v dd e v ss 32 lba wr v ddq v pp w g gd baa rp ai02656b v ssq m58bf008
3/14 AN1269 - application note mpc555 bus architecture the mpc555's bus architecture can be daunting on first appearance. there are many control lines to allow for 8-bit accesses, 16-bit accesses, 32-bit accesses, bus arbitration, etc. many applications do not need to make use of these features. only a simple connection is considered here. the mpc555 can be configured as big-endian or little-endian, with the normal configuration being big- endian. the m58bf008 part is little-endian insofar as the hexadecimal data used to control the command interface uses d0 to equate to the lsb. to use the m58bf008 in the big-endian mode of the mpc555 the address bus and the data bus should be reversed; a29 on the mpc555 should be connected to a0 of the m58bf008, a28 to a1, a17 to a2, etc.; d31 on the mpc555 should be connected to d0 on the m58bf008, d30 to d1, d29 to d2, etc. if this convention is followed then the standard c code drivers for the m58bf008 will not have to be changed. if this convention is not followed then the data for the command interface will need translating for the before the memorys command interface will respond correctly and continuous data in the processors address space will cross through each block of the m58bf008 in turn. the mpc555s memory controller includes control lines that are suitable for connecting to the m58bf008 in either synchronous or asynchronous mode, or both, without the need for glue logic. each transfer is ini- tiated with the address being placed on the address bus, transfer start (ts ) low and the chip select (csx ) low during the rising edge of the system clock. output enable (oe ) or write enable/byte enable (we /be 0) falls low to indicate a read or a write. in burst read operations burst data in progress (bdip ) indicates that the memory should advance the address and read/write (rd/wr ) gives advance notice that the burst operation is a read or a write (the mpc555 never uses burst write operations, but other bus masters are allowed to). burst operations on the mpc555 read from sequential (not interleaved) addresses. for example, if a 32- bit wide burst operation starts from address 1234h, the next address read will be 1238h, followed by 123ch. the mpc555 does not issue continuous or wrapped burst operations, so in the example the fourth burst (to address 1240h) would only occur as part a separate operation. up to four 32-bit reads are pos- sible in one burst operation, but only when the four lsbs of the address start at 0000b (i.e. from address 1230h in the example). although the mpc555 is a 3.3v processor, its external bus is 5v tolerant. 5v parts can be connected to the external bus without the need for transceivers. the short rise and fall times mean that the timings when connecting to 5v parts are not significantly different, though some extra consideration may be required for rising signals. table 1 gives a summary of the input/output dc characteristics on the high and low voltage levels and shows that they are compatible. table 1. input/output dc characteristics comparison booting the mpc555 from external flash the boot mode of the mpc555 is selected by driving the data bus into a specific state during reset with reset configuration (rstconf /texp) low. to boot from an external memory (e.g. flash) the internal flash should be disabled (d20 low), the external boot should be enabled (d3 low) and the boot port size should be set to the memory width (d4-5 both low for 32-bit width). comment mpc555 m58bf008 mpc555 low input from m58bf008 v il3m 0.8v max v ol 0.2v max mpc555 high input from m58bf008 v ih3m 2v min v oh 3.1v min m58bf008 low input from mpc555 v ol3m 0.5v max v il 0.8v max m58bf008 high input from mpc555 v oh3m 2.4v min v ih 2v min
AN1269 - application note 4/14 for an external boot the mpc555 uses chip select 0 (cs0 ) to select the boot memory; cs0 is active (low) for every memory address during the boot process until the registers that configure it are changed. 15 wait states are selected and asynchronous read operations are used. after a hardware reset (hreset ) the boot process executes the instruction at address 00000100h. note that this instruction is at memory location 00040h in the m58bf008s address space since it is a 32-bit part. generally the instruction at address 00000100h will be a jump to the location in the mpc555s mem- ory space where the flash will be mapped. from here the boot process can continue, the base registers and option registers can be configured correctly so that other devices on the bus can be accessed. mpc555 to m58bf008 connection figure 2 shows a connection scheme for the mpc555 to m58bf008. in this configuration the m58bf008 can be the boot device. note the reversal of the address bus and the data bus between the two devices to account for the big-endian/little-endian change. also note that a0 of the m58bf008 should be con- nected to a29 of the mpc555; a30 and a31 address words and bytes, they are not used for double-word width devices. if the m58bf008 is not going to be the boot device then any of the other chip selects can be used instead. although gd is shown connected to v ih in this implementation, it can be left floating since it has an internal pull-up resistor that will ensure correct operation. to access the memory correctly the registers in the mpc555 should be set up according to table 4. note that the motorola definition for describing the x-latency and y-latency is different to the stmicroelectronics definition. motorola count the number of clock cycles between two successive accesses, or wait-states, whereas stmicroelectronics count the difference between the clock numbers. so, for example, a 2 wait- state access (scy field of the base register set to 02h) with burst beats of 0 wait-states (bscy field set to 00h) is equivalent to a 3.1.1.1 burst access in stmicroelectronics terms. care should be taken when configuring the memory controller in the mpc555 to ensure that the correct and optimum values are used. figure 2. connection between the mpc555 and the m58bf008 ai03458 18 a0-a17 w m58bf008 e g rp data31-data0 addr29-addr11 mpc555 sreset we/be0 cs0 dq0-dq31 oe clk clkout lba ts wr rd/wr baa bdip gd v ih
5/14 AN1269 - application note mpc555 bus configuration registers three registers are used to configure the bus on the mpc555. for each chip select there are two registers, a base register and an option register; additionally, to enable burst operations the bbc module config- uration register must be configured correctly. the bits in each of these registers is described in detail in the mpc555 user manual; the description here is tailored specifically to using the mpc555 with an m58bf008. table 2 gives an description of the base register bits and table 3 gives a description of the option register bits.
AN1269 - application note 6/14 table 2. base register description note: the bits here are numbered according to the motorola mpc555 definition; bit 0 is the msb and bit 31 is the lsb. bit(s) mnemonic name description 0-16 ba base address the upper bits of the address are compared to the bits in this register. bits that are masked in the option register do not affect the output of the comparison. if all the unmasked bits match then the corresponding chip mpc555 selected the device attached to it. each chip select is active throughout a 64 kbyte or more section of the memory. if the m58bf008 is using the chip select then these bits set the address where the m58bf008 is mapped in the mpc555 memory space. 17-19 at address type these bits select whether the device on the chip select should respond to all types of access (instruction/data, user/supervisor, etc.) or not. the mask in the option register controls whether the address type is ignored or not. 20-21 ps port size the port size determines whether an 8-bit, 16-bit or 32-bit device is connected to the data bus. the m58bf008 is a 32-bit memory and should use the 32-bit port setting (00b). 22 reserved 23 wp write protect the device can be designated as read-only through this bit. the m58bf008 can be written to and, even if the user wanted to protect the memory, it is not advisable to use this method to protect it as it would disable other features, such as read electronic signature. the m58bf008 should be configured as a read/write part for usual operation. 24-25 reserved 26 webs write-enable/ byte select the output pins we n/be n can either be used to select individual bytes in a word or double-word or as a write enable line. in the m58bf008 it is not possible to select individual bytes, therefore the pins should be configured as write enable outputs. 27 tbdip toggle burst data in progress determines how long the bdip output will be low during each data beat of a burst cycle. the correct setting for the m58bf008 is 0. 28 lbdip late burst data in progress the bdip output can be configured to go low at the start of the burst transfer or after the x-latency has expired. some devices require bdip late in order to trigger the output of the data and update of their internal address register at the correct time. the m58bf008 however will ignore the baa input until the preconfigured x-latency has expired. the recommended setting is for bdip early, though both will work. (bdip early alleviates the need to check the timing!) 29 seta external transfer acknowledge some devices can set the ta on the mpc555 pin to acknowledge the end of a transfer. the m58bf008 does not generate this signal, the internally generated signal from the mpc555 memory controller will terminate the cycle at the correct time. 30 bi burst inhibit the memory controller in the mpc555 needs to be told whether the device can support burst transfers or not. the mpc555 does support burst transfers. when used in asynchronous mode this bit should be set to 1 to inhibit the burst, in burst mode set this bit to 0 to enable the burst. 31 v valid bit the valid bit configures the memory controller to use this chip select. the bit should be set to 1.
7/14 AN1269 - application note table 3. option register description the recommended settings for the registers are summarized in table 4. table 4. mpc555 memory controller register settings summary note: the scy field of the option register (bits 24-27) is set to 2 for 3-1-1-1 access and 3 for 4-1-1-1 access. the m58bf008 can operate at 4-1-1-1 with a maximum clock frequency of 40mhz and at 3-1-1-1 with a maximum clock frequency of 33mhz clock. other connection schemes can be used to control the m58bf008. this scheme is the recommended tech- nique, but other connections are discussed in the examples that follow. bit(s) mnemonic name description 0-16 am address mask the address mask is used in conjunction with the base address in the base register to select the address region where the chip select is active. a bit set to 1 indicated that this address bit is used. use these bits, in conjunction with the base address to map the m58bf008 in the correct memory space. the m58bf008 occupies an address space of 1 mbyte in the memory space of the mpc555, so typically the address mask would be set to fff0h. 17-19 amt address type mask the address mask allows more than one type of address space to be assigned to a single chip select. if the m58bf008 is to be used for instructions and data, in user and supervisor modes and for normal and special transfers then all bits should be masked (set to 0). 20 csnt chip select negation time the chip select negation time can be changed to ensure that the device releases the bus in time for the next device to drive it and avoid bus contention. the recommended setting for the m58bf008 is 0, normal negation time. 21-22 acs address to chip select setup the chip select can be configured to be set up at the same time as the address, or after the address has been set up. to meet the timings of the m58bf008 it is essential to set the chip select up as early as possible, therefore the 00 setting should be used. 23 ehtr extended hold time on read it is possible to have an extra idle cycle inserted between reads and writes in difference memory controller bank. this avoid bus contention for parts that drive the bus sooner than others release it. the m58bf008 is fast enough so that it does not require an additional cycle (though other devices may require the extra cycle; their ehtr registers must be set correctly). 24-27 scy cycle length the cycle length is the number of wait-states required to access the device. in burst transfers this number is determined by the x-latency. see table 4 for the recommended values. 28-30 bscy burst beats length the burst beats length is the number of wait-states required to access the device between burst beats. it is determined by the y-latency. see table 4 for the recommended values. 31 trlx timing relaxed normal or relaxed timings can be selected using this bit. the m58bf008 does not require relaxed timings (which are slower) so a value of 0 should be used. symbol register bits asynchronous synchronous 2 wait-states 3 wait-states 3.1.1.1 4.1.1.1 brx base register 20-31 003h 003h 001h 001h orx option register 20-31 020h 030h 020h 030h bbcmcr burst buffer controller module configuration register 18 x x 1 1
AN1269 - application note 8/14 example bus operations the following sections go into detail regarding the bus operations and signal interactions between the mpc555 and the m58bf008. each section gives an example waveform and timing information. some al- ternative connection details are shown for designers who are trying to use the m58bf008 as a replacement part in an circuit containing an mpc555. for new designs the recommended connections should be used. asynchronous burst read example figure 3 shows an asynchronous read access with three wait-states. the mpc555 sets up the address and activates the chip select ready for cycle 1 of its synchronous clock. the m58bf008 does not wait for the clock in asynchronous mode and starts fetching the data immediately. after tavqv and telqv (both 90ns) the data becomes valid; the mpc555 latches the data on the rising edge of clock cycle 5. under zero wait-state operation the data is latched on clock cycle 2. the critical timing in this example is telqv. for a 40mhz clock (and a 40mhz mpc555) the chip select activates 14ns (timing 19) after clock cycle 0. the data must be setup 6ns (timing 17) before clock cycle 5. using 3 wait-states clock cycle 5 is 125ns after clock cycle 0, with 14ns before the chip select and the data needing to be ready 6ns before the clock rising telqv needs to be 105ns or less. the m58bf008 guarantees telqv less than 90ns. the tavqv is not required for the analysis since the address is set up 13ns (timing 8) after clock cycle 0, 1ns before the chip select; tavqv is also 90ns for the m58bf008. for an mpc555 running at 33mhz only 2 wait-states are required. at boot time the mpc555 uses 15 wait-states to read the boot memory. the m58bf008 boots in asynchronous mode; the 15-wait state latency is more than sufficient to successfully boot the mpc555 using an m58bf008. figure 3. example asynchronous read access synchronous burst read example the m58bf008 toggles between asynchronous and synchronous each time the 60h command is written to the command interface; before the first synchronous access is performed the memory must be toggled from asynchronous to synchronous mode. figure 4 shows the waveforms for a synchronous burst read access with four beats. the mpc555 starts by placing the address on the address bus, activating transfer start (ts ), chip select 0 (cs0 ), output enable (oe ) and burst data in progress (bdip ). the memory uses ts to latch the address and latch the first address of the burst. after the x-latency q1 is output on the data bus; q2, q3 and q4 follow on the subsequent clock cycles. finally chip select 0 (cs0 ) rises to terminate the burst. ai03463 dq0-dq31 a0-a17 e g clk 2 1 0 q1 3 4567 q1 oe cs0 clkout m58bf008 nomenclature mpc555 nomenclature addr29- addr11 data31- data0 tavqv, telqv
9/14 AN1269 - application note figure 4. example 3-1-1-1 synchronous burst read access with 4 data beats from figure 4 it is clear that the signals generated by the mpc555 can be used to access the m58bf008. by examining the timing requirements of the m58bf008 and comparing them to those of the mpc555 it can be shown that both the 33mhz timings and the 40mhz timings match. table 5 shows the timings of the critical timing parameters. table 5. synchronous burst timing requirements m58bf008 mpc555 symbol timing 33mhz 40mhz t avch min 8 15 12 t blch min 8 15 12 t chbh min 3 7 6 t glch min 10 19 17 t elch min 8 14 11 t wrhch min 8 15 12 t chqv 18 max 24 max 19 t chqx2 5 min 1 min 1 ai03461 dq0-dq31 a0-a17 lba e g clk 2 1 0 q1 baa 3 4567 q2 q3 q4 q1 ts oe cs0 bdip clkout m58bf008 nomenclature mpc555 nomenclature addr29- addr11 data31- data0 late bdip
AN1269 - application note 10/14 asynchronous write example all bus operations from the mpc555 are synchronous with its clock. however, m58bf008 parts that are configured for asynchronous write operations ignore the clk input and are accessed in an asynchronous manner. figure 5 shows the signal waveforms for the recommended connections; three wait-states are shown. the mpc555 starts by placing the address on the address bus, activating transfer start (ts ), chip select 0 (cs0 ) and read/write (rd/wr ). write enable (we ) is asserted (low) after the address is latched to indicate a write operation and the data to be written is placed on the data bus. after the wait-states have expired the mpc555 drives we0 and cs0 high to indicate the end of the cycle before changing the ad- dress and data on the bus. from figure 5 it is clear that the signals generated by the mpc555 can be used to access the m58bf008. by examining the timing requirements of the m58bf008 and comparing them to those of the mpc555 the number of wait-states required can be found; table 2 shows the timings of the critical timing parameters. table 6. asynchronous write timing requirements note that the timings in table 6 show that back-to-back write operations to the flash are not possible, oth- erwise the t whwl timing is violated. it will be necessary to ensure that software does not try to perform back-to-back write operations, an extra delay (such as a non-cached nop) may be required between writes to ensure correct operation. also note that 3 wait-states are required to meet the asynchronous timing requirements at 40mhz and 2 wait-states at 33mhz. if the m58bf008 used has been factory configured for asynchronous write operations then w r, baa and lba are ignored during write operations. this allows various changes to the recommended connection technique to be made without loss of performance. for example: 1. the w r pin on the m58bf008 can be left disconnected. a weak pull-up inside the m58bf008 will en- sure that the internal level is v ih , enabling the read operations to be performed correctly. 2. the w r pin on the m58bf008 can be connected to we0 pin on the mpc555. since the w r input is ignored in asynchronous operations it will not affect the write operation. 3. the w pin on the m58bf008 can be connected to the rd /wr pin of the mpc555, though in this case back-to-back writes are still not possible. care should be taken because there are situations where cs0 is only high for the briefest instant of time and this can be missed by the m58bf008. so long as other accesses are performed in the meantime this solution will work correctly. note that tying the w pin on the m58bf008 to ground will not allow the part to work correctly since a write operation will be selected whenever the part is accessed, including when read operations are intended. m58bf008 mpc555 symbol timing 2-wait states, 33mhz 3-wait states, 40mhz t avav min 70 112 113 t wlwh min 70 105 92 t dvwh min 70 75 87 t whwl min 30 19 19
11/14 AN1269 - application note figure 5. example asynchronous write access synchronous write example from the perspective of the mpc555 all writes are synchronous. the waveforms for synchronous write are the same as those for asynchronous writes. therefore, the waveforms in figure 5, asynchronous write access, are equally valid for synchronous write operations. the timing of the m58bf008 parts that have been factory configured for synchronous write operations have different timing requirements. table 7 shows the timings of the critical parameters for synchronous write operations. ai03462 dq0-dq31 a0-a17 lba e g clk 2 1 0 q1 baa 3 4 q1 ts oe cs0 bdip clkout m58bf008 nomenclature mpc555 nomenclature addr29- addr11 data31- data0 w we0 wr rd/wr 5
AN1269 - application note 12/14 table 7. synchronous write timing requirements if the m58bf008 used has been factory configured for synchronous write operations then all the connec- tions are required for correct operation. however, there are still times when some of the pins are ignored. this allows various changes to the recommended connection technique to be made without loss of per- formance. for example: 1. the w pin of the m58bf008 can be connected to the rdwr pin of the mpc555. this solution will cor- rectly control the write enable signal of the m58bf008, so long as back-to-back writes are not per- formed to the m58bf008 by the mpc555. 2. the w pin may be tied to ground. the m58bf008 will work correctly because the rdwr pin will initiate the correct read or write cycle, w will be ignored. the mpc555 can still boot from the m58bf008 since rdwr is high during reset and remains high while the boot code is executed. it is essential to have w r connected, otherwise the addresses cannot be latched correctly during a write cycle (the internal pull-up would always select a read operation). w r cannot be connected to we0 be- cause we0 is too late for the addresses to be latched correctly during a write cycle. m58bf008 mpc555 symbol timing 33mhz 40mhz t avch min 8 15 12 t blch min 8 15 12 t chbh min 3 7 6 t wrlch min 8 15 12 t wlch min 8 19 17 t chwh min 3 11 6 t qvch min 8 15 12 t chqx min 5 7 6 t elch min 8 16 14
13/14 AN1269 - application note stmicroelectronics software drivers stmicroelectronics provide a set of drivers, written in c, manipulating all of the functions of the m58bf008. these are contained in a separate application note. in order to use the c code drivers two additional c functions have to be written by the developer, flashread() is used to tell the software driv- ers how to read from the memory and flashwrite() is used to tell the software drivers how to write to the memory. the drivers include example flashread() and flashwrite() functions and these, combined with set- ting the correct base_addr macro are suitable for use with the mpc555. the example functions are: #define base_addr ((volatile unsigned long*)0x00000000l) . unsigned long flashread( unsigned long uloff ) { return base_addr[uloff]; } static unsigned long flashwrite( unsigned long uloff, unsigned long uval ) { return base_addr[uloff] = uval; } . the drivers also provide an example of these functions as macros to speed up the code execution (since no function call overhead is required). when used with the mpc555 the flashread() function can be replaced with the macro: #define flashread( uloff ) ( base_addr[uloff] ) the flashwrite() function should not be replaced with a macro or an inline function (c++). the use of a function call for each write to the flash will prevent back-to-back writes from occurring; even with this measure, c programmer should look carefully at the assembled code to ensure that no back-to-back writes occur. the time taken to put the parameters on the stack and make the call will be sufficient for the m58bf008 to recover. in terms of the cpu overhead this causes it will be minimal; programming is the time when the most write accesses to the flash occur and each double-word takes about 10 m s to program compared to an additional 200ns (roughly) in the write access. conclusion the m58bf008 can be connected to the mpc555 in a glue-less configuration, providing burst perfor- mance. the flash can be used to boot the mpc555 and does not require shadow ram, code can be ex- ecuted directly from the flash without loss of performance. revision history date version revision details december 2000 -01 first issue february 2001 -02 addition of the dc characteristics comparison. other minor corrections
AN1269 - application note 14/14 if you have any questions or suggestion concerning the matters raised in this document please send them to the following electronic mail address: ask.memory@st.com (for general enquiries) please remember to include your name, company, location, telephone number and fax number. information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners ? 2001 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. www.st.com

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